koulib@sh.itjust.works to Linux@lemmy.mlEnglish · 5 days agoWhich new Protocol or Standard are you most excited about?message-squaremessage-square53fedilinkarrow-up188arrow-down13file-text
arrow-up185arrow-down1message-squareWhich new Protocol or Standard are you most excited about?koulib@sh.itjust.works to Linux@lemmy.mlEnglish · 5 days agomessage-square53fedilinkfile-text
minus-squaredeur@feddit.nllinkfedilinkarrow-up20·edit-25 days agoIn principle it’s just “slimmer ARM”. RISC-V is also extremely dedicated to using memory mapped IO rather than older style IO x86_64 supports. Think lots of registers, a fun zero register that is always zero, and memory mapped IO.
minus-squaremvirts@lemmy.worldlinkfedilinkarrow-up5·5 days agoI for one think we need a register for each unsigned integer, why is zero so special? :P Or if we can’t get that, at least every power of 2 and power of 2 minus 1. Maybe I can submit a proposal for risc-VI 🤣
minus-squarePetteriPano@lemmy.worldlinkfedilinkarrow-up9·5 days ago Maybe I can submit a proposal for risc-VI 🤣 No need! You can make your own custom extension! If the silicon doesn’t support it, then you can provide firmware to emulate it.
minus-squareporl@lemmy.worldlinkfedilinkEnglisharrow-up5·5 days agoI think a register for each of the primes should be enough.
minus-squarecaseyweederman@lemmy.calinkfedilinkarrow-up3·5 days agoARM is also reduced-instruction set but I don’t know how they differ. Is the instruction set somehow more reduced?
minus-squareMonkderVierte@lemmy.mllinkfedilinkarrow-up3·4 days agoAren’t they more like a hybrid instruction set and architecture?
In principle it’s just “slimmer ARM”. RISC-V is also extremely dedicated to using memory mapped IO rather than older style IO x86_64 supports.
Think lots of registers, a fun zero register that is always zero, and memory mapped IO.
I for one think we need a register for each unsigned integer, why is zero so special? :P
Or if we can’t get that, at least every power of 2 and power of 2 minus 1.
Maybe I can submit a proposal for risc-VI 🤣
No need! You can make your own custom extension! If the silicon doesn’t support it, then you can provide firmware to emulate it.
I think a register for each of the primes should be enough.
ARM is also reduced-instruction set but I don’t know how they differ. Is the instruction set somehow more reduced?
Aren’t they more like a hybrid instruction set and architecture?